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MC143416

Dual 16-Bit Linear Codec-Filter

Freescale Semiconductor 

Freescale Semiconductor, Inc.

SERIAL TIMING DESCRIPTION

Synchronous Serial Interface Ports

Digital data and control information is transmitted and re-

ceived through the Synchronous Serial Interface (SSI) ports.

The ports and their modes of operation can be configured by

hardware pins and software controls. This offers greater flex-

ibility to accommodate different hosts, data formats, and data

lengths (size).

The MC143416 uses two synchronous serial interfaces.

These interfaces consist of four pins each: SCLK, STx, SRx,

and SSYNC. The timing relationship of these pins can be

seen in Figure 5. The output serial data is registered on the

rising edge of SCLK so that each input bit can be sampled on

the falling edge of SCLK. The SSIs can be operated in 24–bit

or 16–bit, Dual SSI or Single SSI, long frame or short frame.

The primary difference between these modes is the number

of frames per sampling period and the organization of the

words. The serial ports can be configured through three inde-

pendent pins: SSIDS (data size), SSIFM (framing mode),

and SSIMS (mode select). These pins need to be perma-

nently tied to either DGND or DVDD. The pins are global con-

trols applied on both serial ports according to Table 10.

Pin

SSIDS

SSIMS

SSIFM

Table 10. SSI Configuration Pins

Level

Configuration

0 24 Bits per Frame

1 16 Bits per Frame

0 Dual Serial Mode: Each codec is operated

from an independent serial interface. The

timing of each interface is dictated by the

associated codec timing.

1 Single Serial Mode: Utilizes only SSI0. The

timing of SSI0 is derived from the timing of

the faster of the two codecs. The faster

codec is defined by bit SSI_SEL in control

register 4.

0 Short Frame Mode

1 Long Frame Mode

Data Size — 16–Bit Mode and 24–Bit Mode: The data

size can be selected by the state of the pin SSIDS. When the

pin is tied low, the 24–bit data format is effective. In 24–bit

operation, the control data and register data (bits 23:16) al-

ternately precede the data sample (bits 15:0) in each frame.

See Figures 6 and 8. When this pin is set high, the serial data

format is adjusted to accommodate 16–bit data. In 16–bit op-

eration, the control data and register data are coupled into

one frame, and the data sample is contained in a separate

frame. See Figures 7 and 9.The ordering of the data words

depends on whether the device is in Dual or Single SSI

mode.

Data Mode — Dual SSI Mode and Single SSI Mode:

The SSIMS pin is used to select either Dual SSI mode or

Single SSI mode. When SSIMS is low, the device operates in

Dual SSI mode, and when SSIMS is high, the device oper-

ates in Single SSI mode. In Dual SSI mode, each codec op-

erates through an independent serial interface (Codec 0

operates through SSI0, and Codec 1 operates through

SSI1). The timing of each serial interface is directly related to

the timing of its associated codec (bit clock has the same fre-

quency as the oversampling clock). In Single SSI mode, both

codecs operate from a single SSI interface (SSI0), and the

serial interface timing is dictated by the faster of the two co-

decs. When in this mode, the SRx1 input should be tied to

ground, and the SSI1 port is not functional.

Frame Mode — Long Frame Sync Mode and Short

Frame Sync Mode: This device is able to generate both

long and short framing signals depending on the state of the

pin SSIFM. When SSIFM is low, the device operates in Short

Frame mode, which is defined as a one–bit–wide clock pulse

occurring before the first bit of the data stream (MSB). When

SSIFM is high, the device operates in Long Frame mode. In

this mode, the framing pulse rises simultaneously with the

first data bit (MSB) and falls after the last data bit (LSB) has

been shifted out. The different framing modes are shown in

Figure 5.

SSYNC

(SHORT FRAME)

SSYNC

(LONG FRAME)

SCLK

STx

SRx

HIGH-Z MSB

MSB

DATA IS SHIFTED ON THE RISING EDGE OF CLK

DATA IS SAMPLED INTERNALLY ON THE FALLING EDGE OF CLK

Figure 5. Serial Interface Timing

LSB

LSB

HIGH-Z

MSB

MSB

MC143416

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Go to: www.freescale.com

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