APU0071-002WE-TY 데이터 시트보기 (PDF) - Anpec Electronics
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APU0071-002WE-TY Datasheet PDF : 28 Pages
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APU0071
Table 3. Instruction Table
Instruction Code
Execution
Instruction
RS R / W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
time
(fOSC=270
kHz)
Write “20H” to DDRAM and
Clear Display
0 0 0 0 0 0 0 0 0 1 set DDRAM address to
“00H” from AC.
629µs
Set DDRAM address to
“00H” from AC and return
Return Home
0
0
0000001
∗
cursor to its original
position if shifted. The
629µs
contents of DDRAM are not
changed.
Assign cursor moving
Entry Mode Set
0 0 0 0 0 0 0 1 I / D S direction and enable entire 37µs
display shift.
All display (D) , cursor (C) ,
Display ON / OFF
Control
0
0
0
0
0
0
1
D
C
B
and blinking of cursor
position character on / off
37µs
control bit (B) .
Cursor and Display shift
Cursor or Display
Shift
0
0
0
0
0
1
S/
C
R/L
∗
∗
and their direction control
without changing DDRAM
37µs
data.
Set interface data length
Function Set
0
0
0
0
1 DL A
∗
M1
M0
(DL) , DDRAM addressing
mode (A) and COM / SEG
37µs
output pattern (M0, M1) .
SetCGRAMAddress 0
0
0
1
∗
AC4
AC3
AC2
AC1
AC0
Set CGRAM address in
address counter.
37µs
SetDDRAMAddress 0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address in
address counter.
37µs
Read Busty DDRAM
Whether in internal
AC6 AC5 AC4 AC3 AC2 AC1 AC0 operation or not can be
Flag and
0 1 BF
known by reading BF. The
0µs
Address
CGRAM
∗
∗
AC4 AC3 AC2 AC1 AC0 contents of address
counter can also be read.
Write Data DDRAM
to RAM
CGRAM
1
0
D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal
∗ ∗ ∗ D4 D3 D2 D1 D0 RAM (DDRAM / CGRAM) .
43µs
Read Data DDRAM
from RAM CGRAM
1
1
D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal
∗ ∗ ∗ D4 D3 D2 D1 D0 RAM (DDRAM / CGRAM) .
43µs
I / D = 1 : Increment,
S = 1 : Shift enable,
S / C = 1 : Display shift,
R / L = 1 : Shift right,
D / L = 1 : 8 bit interface,
A = 0 : DDRAM addressing mode 0,
M0 = 0 : Bottom view,
M1 = 0 : No Rotate,
BF = 1 : System is in operation
I / D = 0 : Decrement
S = 0 : Shift disable
S / C = 0 : Move cursor
R / L = 0 : Shift left
D / L = 0 : 4-bit interface
A = 1 : DDRAM addressing mode1
M0 = 1 : Top view
M1 = 1 : Rotate
BF = 0 : System is ready
Copyright ANPEC Electronics Corp.
10
Rev. A.07 - FEB., 2002
www.anpec.com.tw
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