MAX6370KA 데이터 시트보기 (PDF) - Maxim Integrated

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MAX6370KA

Pin-Selectable Watchdog Timers

Maxim Integrated 

Pin-Selectable Watchdog Timers

Pin Description

PIN NAME

FUNCTION

Watchdog Input. If WDI remains either high or low for the duration of the watchdog timeout period (tWD), WDO

1

WDI triggers a pulse. The internal watchdog timer clears whenever a WDO is asserted or whenever WDI sees a

rising or falling edge.

2

GND Ground

3

N.C. Not Connected. Do not make any connection to this pin.

4

SET0 Set Zero. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.

5

SET1 Set One. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.

6

SET2 Set Two. Logic input for selecting startup delay and watchdog timeout periods. See Table 1 for timing details.

Watchdog Output. Pulses low for the watchdog output pulse width, tWDO, when the internal watchdog times

7

WDO out. The MAX6369/MAX6371/MAX6373 have open-drain outputs and require a pull-up resistor. The

MAX6370/MAX6372/MAX6374 outputs are push-pull.

8

VCC Supply Voltage (+2.5V to +5.5V)

Table 1. Minimum Timeout Settings

LOGIC INPUTS

SET2 SET1 SET0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

MAX6369/MAX6370

tDELAY, tWD

1ms

10ms

30ms

Disabled

100ms

1s

10s

60s

MAX6371/MAX6372

tDELAY = 60s, tWD

1ms

3ms

10ms

Disabled

100ms

300ms

3s

60s

MAX6373/MAX6374

tDELAY

tWD

3ms

3s

60s

Disabled

200µs

First Edge

First Edge

60s

3ms

3s

1s

Disabled

30µs

1s

10s

10s

Detailed Description

The MAX6369–MAX6374 are flexible watchdog circuits

for monitoring µP activity. During normal operation, the

internal timer is cleared each time the µP toggles the

WDI with a valid logic transition (low to high or high to

low) within the selected timeout period (tWD). The WDO

remains high as long as the input is strobed within the

selected timeout period. If the input is not strobed

before the timeout period expires, the watchdog output

is asserted low for the watchdog output pulse width

(tWDO). The device type and the state of the three logic

control pins (SET0, SET1, and SET2) determine watch-

dog timing characteristics. The three basic timing varia-

tions for the watchdog startup delay and the normal

watchdog timeout period are summarized below (see

Table 1 for the timeout characteristics for all devices in

the family):

• Watchdog Startup Delay:

Provides an initial delay before the watchdog timer is

started.

Allows time for the µP system to power up and initial-

ize before assuming responsibility for normal watch-

dog timer updates.

Includes several fixed or pin-selectable startup delay

options from 200µs to 60s, and an option to wait for

the first watchdog input transition before starting the

watchdog timer.

_______________________________________________________________________________________ 5

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