MAX5018 데이터 시트보기 (PDF) - Maxim Integrated

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MAX5018

8-Bit, High-Speed DAC

Maxim Integrated 

8-Bit, High-Speed DAC

Figure 3. Reference Buffer and DAC Output Circuit

sinks convert the registered data into the appropriate

analog output. When FT is tied high, the control inputs

and data are not registered. The analog output asyn-

chronously tracks the input data and video controls.

Feedthrough itself is asynchronous and is usually used

as a DC control.

To be registered synchronously, control and data inputs

must be present at the input pins for a specific setup

time (ts) before and a specific hold time (tH) after

CONV’s rising edge. Setup and hold times are not impor-

tant in asynchronous mode. The minimum pulse widths

high (tPWH) and low (tPWL), as well as settling time,

become the limiting factors (Figure 4).

The video controls produce the output levels needed

for horizontal blanking, frame synchronization, etc., to

be compatible with video-system standards as

described in RS-343-A. Table 2 shows the video-

control effects on the analog output. Internal logic gov-

erns blank, sync, and force high so that they override

the data inputs as needed in video applications. Sync

overrides both the data and other controls to produce

full negative video output (Figure 5).

Reference-white, video-level output is provided by force

high, which drives the internal digital data to full-scale

output (100IRE units). Bright gives an additional 10% of

full-scale value to the output level. This function can be

used in graphic displays for highlighting menus, cursors,

or warning messages. If the devices are used in non-

video applications, the video controls can be left open.

Convert Clock

For best performance, the clock should be differentially

ECL driven by using CONV and CONV (Figure 6).

Driving the clock in this manner minimizes clock noise

and power-supply/output intermodulation. The clock’s

rising edge synchronizes the data and control inputs to

the MAX5018. Since CONV determines the actual

switching threshold of CONV, the clock can be driven

single-ended by connecting a bias voltage to CONV.

This bias voltage sets the converter clock’s switching

threshold.

Analog Outputs

The MAX5018 has two analog outputs that are high-

impedance, complementary current sinks. The outputs

vary in proportion to the input data, controls, and refer-

ence-current values so that the full-scale output can be

changed by setting ISet.

In video applications, the outputs can drive a doubly

terminated 50Ω or 75Ω load to standard video levels. In

the standard configuration shown in Figure 7, the out-

put voltage is the product of the output current and

load impedance and is between 0V and -1.07V. Out-

(Figure 5) provides a video output waveform with the

Sync pulse bottom at -1.07V. Out+ is inverted with

Sync up.

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