LH543601 데이터 시트보기 (PDF) - Sharp Electronics
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LH543601 Datasheet PDF : 43 Pages
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LH543601
256 × 36 × 2 Bidirectional FIFO
FUNCTIONAL DESCRIPTION (cont’d)
Two mailbox registers provide a separate path for
passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is syn-
chronized to the reading port’s clock. This mailbox func-
tion facilitates the synchronization of data transfers
between asynchronous systems.
Data-bypass mode allows Port A to directly transfer
data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-
PIN CONNECTIONS
tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.
A word-width-select option is provided on Port B for
36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utiliza-
tion of bus bandwidths.
A Byte Parity Check Flag at each port monitors data
integrity. Control-Register bit 0 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired.
VCCO
18
D10A
19
D9A
20
D8A
21
VSSO
22
D7A
23
D6A
24
D5A
25
VCCO
26
D4A
27
D3A
28
D2A
29
VSSO
30
D1A
31
D0A
32
RS
33
RT1
34
D0B
35
D1B
36
D2B
37
VSSO
38
D3B
39
D4B
40
D5B
41
VCCO
42
D6B
43
D7B
44
D8B
45
VSSO
46
D9B
47
D10B
48
D11B
49
VCCO
50
CHAMFERED
EDGE
TOP VIEW
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
VCCO
D24A
D25A
D26A
VSSO
D27A
D28A
D29A
VCCO
D30A
D31A
D32A
VSSO
D33A
D34A
D35A
RT2
VSS
D35B
D34B
VSSO
D33B
D32B
D31B
VCCO
D30B
D29B
D28B
VSSO
D27B
D26B
D25B
VCCO
Figure 1. Pin Connections for 132-Pin PQFP Package
(Top View)
543601-30
2
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