JBT6K47-AS 데이터 시트보기 (PDF) - Toshiba
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JBT6K47-AS Datasheet PDF : 22 Pages
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JBT6K47-AS
Device Operation
· Starting data transfer
A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic
synchronously with the rising edge of CPH, setting the device ready to transfer data. Data transfer
starts at the next rise of CPH.
Also, regardless how many rising edges are existed, DI/O or DO/I recognizes the first rising edge, and
the grayscale data is latched at the next rising edge.
· Data transfer method
The data is latched in from the grayscale bus to the sampling register synchronously with each rising
edge of CPH.
Grayscale data for three outputs are latched into the device simultaneously in one transfer.
Grayscale data are written as three outputs in parallel during one transfer. Data transfer completes
after 88 transfers. Then the device enters Standby mode.
Data written to the sampling register are the operation result of the grayscale data bus.
· Terminating data transfer
The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of
CPH one clock period before the last data is latched in.
The output from this pin can be connected directly as input to the data transfer enable pin (DI/O or
DO/I) of the next stage LCD driver. In this way, multiple devices can be easily cascaded to drive a large
screen.
· Panel drive output
After finishing transferring the grayscale data, the data is latched into the devise when Load is at
High level. The grayscale data of the sampling register is transferred to the load register, and the LCD
panel drive output is switched to the corresponded output to the grayscale data. The load signal
recognizes the data asynchronously with the CPH.
· The grayscale data bus
JBT6K47-AS is capable to determine the valid grayscale data bus by controlling MD pin and GS pin.
The relationship between the MD pin or the GS pin and the valid grayscale data bus is shown below.
Input Low or High for the invalid grayscale data bus.
MD GS
H
L
L
H
L
Grayscale
Data Bus
6-bit mode
4-bit mode
1 bit mode
Colors
26 thousand
colors
4096 colors
8 colors
nIN5
Valid
Valid Grayscale Data Bus
nIN4
nIN3
nIN2
nIN1
Valid
Valid
L/H
L/H
L/H
L/H
L/H
n = X, Y, Z
Note 3: L/H indicates VDD level or VSS level.
: When MD = High, GS = High, the grayscale data bus is set to 4-bit mode.
nIN0
L/H
L/H
11
2002-01-30
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