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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

IN74HC533A 데이터 시트보기 (PDF) - IK Semicon Co., Ltd

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IN74HC533A
IKSEMICON
IK Semicon Co., Ltd IKSEMICON
IN74HC533A Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
IN74HC533A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V 25 °C 85°C 125°C Unit
to
-55°C
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
tPLH, tPHL Maximum Propagation Delay, Latch Enable to Q 2.0 175
220
265
ns
(Figures 2 and 5)
4.5 35
44
53
6.0 30
37
45
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to 2.0 150
190
225
ns
Q (Figures 3 and 6)
4.5 30
38
45
6.0 26
33
38
tPZL, tPZH Maximum Propagation Delay , Output Enable to 2.0 150
190
225
ns
Q (Figures 3 and 6)
4.5 30
38
45
6.0 26
33
38
tTLH, tTHL Maximum Output Transition Time, Any Output 2.0 60
75
90
ns
(Figures 1 and 5)
4.5 12
15
18
6.0 10
13
15
CIN Maximum Input Capacitance
-
10
10
10
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
Power Dissipation Capacitance (Per Latch)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
37
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V 25 °C to -55°C 85°C 125°C Unit
tsu
Minimum Setup Time, Input D to
2.0
75
Latch Enable (Figure 4)
4.5
15
6.0
13
95
110
ns
19
22
16
19
th
Minimum Hold Time, Latch Enable 2.0
5
to Input D(Figure 4)
4.5
5
6.0
5
5
5
ns
5
5
5
5
tw
Minimum Pulse Width, Latch Enable 2.0
80
(Figure 2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall Times 2.0
(Figure 1)
4.5
6.0
1000
500
400
1000 1000
ns
500
500
400
400
Rev. 00

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