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IDT72255L10G

CMOS SUPERSYNC FIFO 8,192 x 18, 16,384 x 18

Integrated Device Technology 

IDT72255/72265 SyncFIFO™

8,192 x 18, 16,384 x 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OUTPUTS:

FULL FLAG (FF/IR)

This is a dual purpose pin. In IDT Standard Mode, the Full

Flag (FF) function is selected. When the FIFO is full (i.e. the

write pointer catches up to the read pointer), FF will go LOW,

inhibiting further write operation. When FF is HIGH, the FIFO

is not full. If no reads are performed after a reset (either MRS

or PRS), FF will go LOW after 8,192 writes tor the IDT72255

and 16,384 writes to the IDT72265.

In FWFT Mode, the Input Ready (IR) function is selected.

IR goes LOW when memory space is available for writing in

data. When there is no longer any free space left, IR goes

HIGH, inhibiting further write operation. If no reads are

performed after a reset (either MRS or PRS), IR will go HIGH

after 8,193 writes for the IDT72255 and 16,385 writes for the

IDT72265.

The IR status not only measures the contents of the FIFO

memory, but also counts the presence of a word in the output

register. Thus, in FWFT mode, the total number of writes

necessary to deassert IR is one greater than needed to assert

FF in IDT Standard mode.

FF/IR is synchronized to WCLK. It is double-registered to

enhance metastable immunity.

EMPTY FLAG (EF/OR)

This is a dual purpose pin. In the IDT Standard Mode, the

Empty Flag (EF) function is selected. When the FIFO is empty

(i.e. the read pointer catches up to the write pointer), EF will go

LOW, inhibiting further read operations. When EF is HIGH, the

FIFO is not empty.

When writing the first word to an empty FIFO, the deassertion

time of EF is variable, and can be represent by the First Word

Latency parameter, tFWL1, which is measured from the rising

WCLK edge that writes the first word to the rising RCLK edge

that updates the flag. tFWL1 includes any delays due to clock

skew and can be expressed as follows:

tFWL1 max. = 10*Tf + 2*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever is

shorter, and TRCLK is the RCLK period. Since no read can

take place until EF goes HIGH, the tFWL1 delay determines

how early the first word can be available at Qn. This delay has

no effect on the reading of subsequent words.

In FWFT Mode, the Ouput Ready (OR) function is selected.

OR goes LOW at the same time that the first word written to an

empty FIFO appears valid on the outputs. OR goes HIGH one

cycle after RCLK shifts the last word from the FIFO memory

to the outputs. Then further data reads are inhibited until OR

goes LOW again.

When writing the first word to an empty FIFO, the assertion

time of OR is variable, and can be represented by the First

Word Latency parameter, tFWL2, which is measured from the

rising WCLK edge that writes the first word to the rising RCLK

edge that updates the flag. tFWL2 includes any delay due to

clock skew and can be expressed as follows:

tFWL2 max. = 10*Tf + 3*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever is

shorter, and TRCLK is the RCLK period. Note that the First

Word Latency in FWFT mode is one RCLK cycle longer than

in IDT Standard mode. The tFWL2 delay determines how early

the first word can be available at Qn. This delay has no effect

on the reading of subsequent words.

EF/OR is sychronized to the RCLK. It is double-registered

to enhance metastable immunity.

72255 – 8,192 x 18–BIT

72265 – 16,384 x 18–BIT

17

12

0 17

13

0

EMPTY OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

EMPTY OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

17

12

0 17

13

0

FULL OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

NOTE:

3037 drw 05

1. Any bits of the offset register not being programmed should be set to zero.

FULL OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

3037 drw 06

Figure 3. Offset Register Location and Default Values

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