IDT6168LA(2001) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT6168LA
(Rev.:2001)

CMOS Static RAM 16K (4K x 4-Bit)

Integrated Device Technology 

IDT6168SA/LA

CMOS Static RAM 16K (4K x 4-Bit)

Military, Industrial, and Co mmercial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,5)

t WC

ADDRESS

t AW

CS

t AS

tWP

t

(3)

WR

WE

DATAOUT

t WHZ (6)

PREVIOUS DATA VALID (4)

t DW

tOW (6)

t DH

(6)

t CHZ

DATA

VALID

(4)

,

DATAIN

DATA VALID

3090 drw 08

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,5)

t WC

ADDRESS

t AW

CS

tAS

WE

(3)

t CW

tWR

t DW

t DH

DATAIN

DATA VALID

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state and input signals should not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high impedance state.

6. Transition is measured ±200mV from steady state.

,

3090 drw 09

6.472

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