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ICS9250-27

Frequency Generator and Integrated Buffers for Celeron & PII/III™

Integrated Device Technology 

ICS9250-27

Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Maximum Allowed Current

815

Condition

Powerdown Mode

(PWRDWN# = 0

Full Active 66MHz

FS[2:0] = 010

Full Active 100MHz

FS[2:0] = 011

Full Active 133MHz

FS[2:0] = 111

Max 2.5V supply consumption Max 2.5V supply consumption

Max discrete cap loads,

Max discrete cap loads,

Vddq2 = 2.625V

Vddq2 = 3.465V

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

10mA

10mA

70mA

280mA

100mA

280mA

Clock Enable Configuration

PD# CPUCLK SDRAM IOAPIC

66MHz

PCICLK

REF,

48MHz

Osc

VCOs

0

LOW

LOW LOW LOW LOW LOW OFF OFF

1

ON

ON

ON

ON

ON

ON ON ON

IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM

3

0395F—01/25/10

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