IZ0065 데이터 시트보기 (PDF) - Integral Corp.
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IZ0065 Datasheet PDF : 6 Pages
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IZ0065
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min Max Unit
Operating Current *
IDD
Supply Current *
IEE
Input High Voltage
VIH
fCL2=400KHz
fCL1=1KHz
-
-
1
mA
-
10
µA
0.7VDD VDD
V
Input Low Voltage
VIL
Input Leakage Current
ILKG
VIN =0-VDD
0
0.3VDD
-5
5
µA
Output High Voltage
Output Low Voltage
Voltage Descending
Leakage Current
VOH
IOH = -0.4mA
VDD-
-
0.4
VOL
IOL = +0.4mA
-
0.4
V
VD1
ION=0.1mA for one of
-
1.1
SC1-SC40
VD2
ION=0.5mA for each
-
1.5
SC1-SC40
IV
VIH= VDD~ VEE
-10
10
µA
(Output SC1-
SC40:floating)
Applicable pin
-
CL1, CL2, DL1,
DL2,
DR1, DR2,
SHL1, SHL2, M,
FCS
DL1, DL2, DR1,
DR2
V(V1-V6),
SC(SC1-SC40)
V1-V6
* VDD-VEE=4V
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol Test Condition
Min Max Unit
Applicable pin
Data Shift Frequency
fCL
-
-
400
KHz
CL2
Clock High Level Width tWCKH
-
800
-
CL1, CL2
Clock Low Level Width
tWCKL
-
800
-
CL2
Clock Set-up Time
tLS
from CL2 to CL1 500
-
tLS
from CL1 to CL2 500
-
ns
CL1, CL2
Clock Rise/Fall Time
tR/tF
-
-
200
Data Set-up Time
tSU
-
300
-
DL1, DL2, DR1,
DR2,
Data Hold Time
tDH
-
300
-
FLM
Data Delay Time
tD
CL=15pF
-
500
DL1, DL2, DR1,
DR2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through
the input circuit to the power supply,To avoid this, input level must be fixed at «H» or «L».
IN T E G R A L
2
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