A617308S-10 데이터 시트보기 (PDF) - AMIC Technology
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A617308S-10 Datasheet PDF : 13 Pages
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A617308 Series
Preliminary
128K X 8 BIT HIGH SPEED CMOS SRAM
Features
n Single + 5V power supply
n Access times: 10/12/15 ns (max.)
n Current: Operating: 150mA (max.)
Standby: 12mA (max.)
n Full static operation, no clock or refreshing required
General Description
The A617308 is a high-speed, low-power 1,048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply. It is built using high performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
n SOJ
n All inputs and outputs are directly TTL compatible
n Common I/O using three-state output
n Data retention voltage: 3V (min.)
n Available in 32-pin SOJ and TSOP packages
Minimum standby power is drawn by this device when
chip enable is disable, independent of the other input
levels.
Data retention is guaranteed at a power supply voltage
as low as 3V.
n TSOP
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O 0
13
I/O 1
14
I/O 2
15
GND
16
32
VCC
31
A15
30
CE2
29
WE
28
A13
27
A8
26 A9
25
A11
24
OE
23
A10
22 CE1
21
I/O 7
20
I/O 6
19
I/O 5
18
I/O 4
17
I/O 3
A11
1
A9
2
A8
3
A13
4
WE
5
CE2
6
A15
7
VCC
8
NC
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
A617308V
32
OE
31
A10
30
CE1
29
I/O 7
28
I/O 6
27
I/O 5
26
I/O 4
25
I/O 3
24
GND
23
I/O 2
22
I/O 1
21
I/O 0
20
A0
19
A1
18
A2
17
A3
PRELIMINARY (January, 2000, Version 0.2)
1
AMIC Technology, Inc.
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