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HEF4069UBPN Datasheet PDF : 17 Pages
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NXP Semiconductors
HEF4069UB
Hex inverter
10. Dynamic characteristics
Table 6. Dynamic characteristics
Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5.
Symbol Parameter
Conditions VDD
Extrapolation formula[1] Min Typ Max Unit
tPHL
HIGH to LOW
propagation delay
nA to nY;
5V
18 ns + (0.55 ns/pF)CL
-
10 V
9 ns + (0.23 ns/pF)CL
-
45
90 ns
20
40 ns
15 V
7 ns + (0.16 ns/pF)CL
-
15
25 ns
tPLH
LOW to HIGH
propagation delay
nA to nY
5V
13 ns + (0.55 ns/pF)CL
-
10 V
9 ns + (0.23 ns/pF)CL
-
40
80 ns
20
40 ns
15 V
7 ns + (0.16 ns/pF)CL
-
15
30 ns
tTHL
HIGH to LOW output output nY
transition time
5V
10 ns + (1.00 ns/pF)CL
-
10 V
9 ns + (0.42 ns/pF)CL
-
60
120 ns
30
60 ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40 ns
tTLH
LOW to HIGH output output nY
transition time
5V
10 ns + (1.00 ns/pF)CL
-
10 V
9 ns + (0.42 ns/pF)CL
-
60
120 ns
30
60 ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40 ns
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 7. Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
PD
dynamic power dissipation 5 V
10 V
15 V
Typical formula
Where
PD = 600 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
PD = 4000 fi + (fo CL) VDD2 (W) fo = output frequency in MHz;
PD = 22000 fi + (fo CL) VDD2 (W) CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4069UB
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 16 November 2011
© NXP B.V. 2011. All rights reserved.
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