HD66764TB0 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HD66764TB0 Datasheet PDF : 38 Pages
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HD66764
Table 1 Pin Functions (cont)
Signal Name
VREGL
VREG1
VREGH
VREG2
VLREF
RESET1*/
RESET2*
CL1
FLM
M
DISPTIMG
DCCLK
CCL
CDA
CCS*
Quantity
1
1
1
1
1
2
1
1
1
1
1
1
1
1
Input/
Output
-
-
-
-
-
Input
Input
Input
Input
Input
Input
Input
Input
Input
Connected to
External
reference
voltage
VREGH
VREG1
VLREF or
open
VREG2 or
external power
supply
External reset
circuit
CL1 of
HD66763
FLM of
HD66763
M of HD66763
DISPTMG of
HD66763
DCCLK of
HD66763
CCL of
HD66763
CDA of
HD66763
CCS* of
HD66763
Function
Reference voltage input. Connect an external
reference voltage. Input current is not supplied
from this pin. Therefore, External voltage can be
generated by regulator which uses divided
resistor.
A voltage that doubles, triples, quadruples, or
quintuples the voltage on VREGL is output here.
Connects the output of VREG1.
A voltage that doubles, triples, quadruples, or
quintuples the voltage on VREGH is output here.
Input for the LCD drive voltage. When the
internal amplification circuit is used, the output of
VREG2 is connected here. When the circuit is
not used, supply external power.
Reset pin. When a low level is input here, the
LSI is reinitialized. Be sure to apply a signal to
this pin during the system’s power-on reset.
RESET1* and RESET2* are equivalent.
So apply a signal to either pin as required and
leave the other pin open.
Clock input pin. The output of the LCD changes
on the falling edge of this signal.
Frame-synchronization with the segment driver.
Inputs the current-alternating signal from the
LCD output. When output is selected, the
following levels are output:
Low: VCL, high: VCH
When output is not selected, VM is output.
A display timing signal.
DISPTMG = 1: display, DISPTMG = 0: non-
display
A clock for the step-up circuit that is supplied
from HD66763.
Operates as a clock for the transfer of register
settings. Latches data on the rising edge of the
clock.
Operates as the data for the transfer of register
settings.
A chip-select signal.
Low: selected (data-transfer enabled), high: not
selected (data-transfer disabled)
7
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