CY7C4201V-15AXC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C4201V-15AXC

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Switching Waveforms (continued)

First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

tDS

D0 –D8

D0 (FIRSTVALID WRITE)

D1

WEN1

tENS

[16]

tFRL

WEN2

(if applicable)

RCLK

EF

tSKEW1

tREF

REN1,

REN2

D2

tA [17]

D3

D4

tA

Q0 –Q8

OE

tOLZ

tOE

D0

D1

Notes:

16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK

+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).

17. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06010 Rev. *B

Page 11 of 18

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