CY7C1041BV33L-25VC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1041BV33L-25VC

256K x 16 Static RAM

Cypress Semiconductor 

CY7C1041BV33

Data Retention Waveform

VCC

3.0V

tCDR

CE

DATA RETENTION MODE

VDR > 2V

Switching Waveforms

[11, 12]

Read Cycle No. 1

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled) [12, 13]

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

Notes:

11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

DATA VALID

3.0V

tR

1041BV33–

DATA VALID

1041BV33-6

tHZOE

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

IISSBB

1041BV33-7

Document #: 38-05168 Rev. **

Page 6 of 11

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