CY2309 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY2309

Low-Cost 3.3V Zero Delay Buffer

Cypress Semiconductor 

CY2305

CY2309

Pin Description for CY2309

Pin

Signal

1

REF[1]

2

CLKA1[2]

3

CLKA2[2]

4

VDD

5

GND

6

CLKB1[2]

7

CLKB2[2]

8

S2[3]

9

S1[3]

10

CLKB3[2]

11

CLKB4[2]

12

GND

13

VDD

14

CLKA3[2]

15

CLKA4[2]

16

CLKOUT[2]

Description

Input reference frequency, 5V-tolerant input

Buffered clock output, Bank A

Buffered clock output, Bank A

3.3V supply

Ground

Buffered clock output, Bank B

Buffered clock output, Bank B

Select input, bit 2

Select input, bit 1

Buffered clock output, Bank B

Buffered clock output, Bank B

Ground

3.3V supply

Buffered clock output, Bank A

Buffered clock output, Bank A

Buffered output, internal feedback on this pin

Pin Description for CY2305

Pin

Signal

1

REF[1]

2

CLK2[2]

3

CLK1[2]

4

GND

5

CLK3[2]

6

VDD

7

CLK4[2]

8

CLKOUT[2]

Description

Input reference frequency, 5V-tolerant input

Buffered clock output

Buffered clock output

Ground

Buffered clock output

3.3V supply

Buffered clock output

Buffered clock output, internal feedback on this pin

Select Input Decoding for CY2309

S2

S1

CLOCK A1–A4 CLOCK B1–B4

0

0

Three-state

Three-state

0

1

Driven

Three-state

1

0

Driven

Driven

1

1

Driven

Driven

CLKOUT[4]

Driven

Driven

Driven

Driven

Output Source

PLL

PLL

Reference

PLL

PLL Shutdown

N

N

Y

N

Notes:

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.

Document #: 38-07140 Rev. *G

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