BSI
BS616LV2020
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269 Ω
3.3V
OUTPUT
1269 Ω
INCLUDING
JIG AND
SCOPE
100PF
1404 Ω
INCLUDING
JIG AND
SCOPE
5PF
1404 Ω
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667 Ω
1.73V
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t AVAX
t AVQV
t E1LQV
t E2LQV
t BA
t GLQV
t ELQX
t BE
t GLQX
t EHQZ
t BDO
t GHQZ
t AXOX
PARAMETER
NAME
t
RC
t AA
t ACS1
t ACS2
t (1)
BA
t OE
t CLZ
t BE
t OLZ
t CHZ
t BDO
t OHZ
t OH
DESCRIPTION
BS616LV2020-70
MIN. TYP. MAX.
Read Cycle Time
70 -- --
Address Access Time
-- -- 70
Chip Select Access Time
(CE1) -- -- 70
Chip Select Access Time
(CE2) --
--
70
Data Byte Control Access Time
(LB,UB) --
--
35
Output Enable to Output Valid
-- -- 35
Chip Select to Output Low Z
(CE1,CE2) 10 --
--
Data Byte Control to Output Low Z (LB,UB) 10 --
--
Output Enable to Output in Low Z
10 -- --
Chip Deselect to Output in High Z (CE1,CE2) 0
-- 35
Data Byte Control to Output High Z (LB, UB) 0
-- 35
Output Disable to Output in High Z
0 -- 30
Output Disable to Address Change
10 -- --
NOTE :
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
tBA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
BS616LV2020-10
MIN. TYP. MAX.
100 -- --
-- -- 100
-- -- 100
-- -- 100
-- -- 50
-- -- 50
15 -- --
15 -- --
15 -- --
0 -- 40
0 -- 40
0 -- 35
15 -- --
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV2020
6
Revision 2.3
April 2002