AV2722 데이터 시트보기 (PDF) - Unspecified
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AV2722 Datasheet PDF : 29 Pages
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AV2722 (Preliminary)
LEFT JUSTIFIED MODE
In Left Justified mode, the MSB of the audio data SDI is sampled on the first rising edge of SC following SFDA/
SFAD transition. SFDA/SFAD are high during the left channel samples and low during the right channel samples.
SFDA (PIN 4) OR
SFAD (PIN 6)
SC (PIN 2)
SDI (PIN 3)
(16-BIT AUDIO DATA)
SDI (PIN 3)
(18-BIT AUDIO DATA)
SDI (PIN 3)
(20-BIT AUDIO DATA)
SDI (PIN 3)
(24-BIT AUDIO DATA)
Left channel
1/fs
Right channel
15 14
MSB
17 16
MSB
19 18
MSB
23 22 21
MSB
210
LSB
15 14
MSB
210
LSB
17 16
MSB
21 0
LSB
19 18
MSB
210
23 22 21
LSB
MSB
"Left Justified" Data Input Timing
210
LSB
210
LSB
21 0
LSB
210
LSB
DSP Mode
In DSP Mode, the audio data SD is in time division multiplexed format. The left and right channel data are shifted
into the chip in sequence with the left channel data first followed by the right channel data. SFDA/SFAD is a “sync”
pulse which appears every 1/fs time. The minimum SFDA/SFAD sync-pulse is one SC cycle.
SFDA (PIN 4) OR
SFAD (PIN6)
SC (PIN 2)
SDI (PIN3)
(16-BIT AUDIO DATA)
SDI (PIN3)
(18-BIT AUDIO DATA)
SDI (PIN3)
(20-BIT AUDIO DATA)
SDI (PIN3)
(24-BIT AUDIO DATA)
1/fs
1 SC
15 14
2
MSB
Left channel
1 0 15 14
210
LSB MSB
Right channel
LSB
15
No valid data
17 16
2 1 0 17 16
210
MSB
Left channel
LSB MSB
Right channel
LSB
17
No valid data
19 18
MSB
Left channel
2 1 0 19 18
LSB MSB
21 0
Right channel
LSB
19
No valid data
23 22 21
MSB
Left channel
2 1 0 23 22 21
LSB MSB
DSP Mode Timing
210
23
Right channel
LSB No valid data
9-29
January 22, 2004
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