NXP Semiconductors
74LVC3G04
Triple inverter
6. Pinning information
6.1 Pinning
74LVC3G04
1A 1
3Y 2
2A 3
GND 4
8 VCC
7 1Y
6 3A
5 2Y
001aad954
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
74LVC3G04
1A 1
8 VCC
3Y 2
7 1Y
2A 3
6 3A
GND 4
5 2Y
001aad955
Transparent top view
Fig 5. Pin configuration SOT833-1 (XSON8)
74LVC3G04
1A 1
3Y 2
8 VCC
7 1Y
2A 3
6 3A
GND 4
5 2Y
001aai254
Transparent top view
Fig 6. Pin configuration SOT996-2 (XSON8U)
terminal 1
index area
74LVC3G04
1Y 1
7 1A
3A 2
6 3Y
2Y 3
5 2A
001aad956
Transparent top view
Fig 7. Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3. Pin description
Symbol
Pin
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
1A, 2A, 3A
1, 3, 6
GND
4
1Y, 2Y, 3Y
7, 5, 2
VCC
8
SOT902-1
7, 5, 2
4
1, 3, 6
8
Description
data input
ground (0 V)
data output
supply voltage
74LVC3G04_7
Product data sheet
Rev. 07 — 16 June 2008
© NXP B.V. 2008. All rights reserved.
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