5962F9563501QYC 데이터 시트보기 (PDF) - Intersil
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5962F9563501QYC Datasheet PDF : 36 Pages
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HS-RTX2010RH
PGA And CQFP
Pin/Signal Assignments (Continued)
CQFP
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
PGA
PIN
L6
L8
K8
L9
L10
K9
L11
K10
J10
K11
J11
H10
H11
F10
G10
G11
G9
F9
F11
SIGNAL
NAME
MA11
MA12
MA13
VDD
MA14
MA15
MA16
MA17
MA18
MA19
GND
LDS
UDS
NEW
BOOT
PCLK
MR/W
MD00
MD01
TYPE
Output; Address Bus
Output; Address Bus
Output; Address Bus
Power
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Ground
Output
Output
Output
Output
Output
Output
I/O; Data Bus
I/O; Data Bus
PGA And CQFP
Pin/Signal Assignments (Continued)
CQFP
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
-
PGA
PIN
E11
E10
E9
D11
D10
C11
B11
C10
A11
B10
B9
A10
A9
B8
A8
B6
B7
A7
C7
C3
SIGNAL
NAME
MD02
MD03
MD04
GND
MD05
MD06
MD07
VDD
MD08
MD09
MD10
MD11
MD12
MD13
MD14
GND
MD15
GA00
GA01
-
TYPE
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Power
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
Output; Address Bus
Output; Address Bus
Isolated Alignment Pin
Output Signal Descriptions
SIGNAL CQFP
OUTPUTS
NEW
60
BOOT
61
MR/W
63
UDS
59
LDS
58
GIO
16
GR/W
15
PCLK
62
TCLK
2
INTA
3
RESET
LEVEL
DESCRIPTION
1 NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress.
1 BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing
bit 3 of the Configuration Register.
1 MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress.
1 UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being
accessed.
1 LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being
accessed.
1 ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress.
1 ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress.
0 PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK.
Held low extra cycles when WAIT is asserted.
0 TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles.
0 INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress.
Input Signal, Bus, and Power Connection Descriptions
SIGNAL
INPUTS
WAIT
ICLK
RESET
CQFP
LEAD
DESCRIPTION
13 WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended.
14 INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels).
12 A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle
setup and hold times.
4
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