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25AA040-E

4K SPI Bus Serial EEPROM

Microchip Technology 

25AA040/25LC040/25C040

3.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25XX040 contains a write enable latch. See

Table 3-3 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WREN instruction will set the

latch, and the WRDI will reset the latch.

The following is a list of conditions under which the

write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

• WP line is low

FIGURE 3-4:

WRITE ENABLE SEQUENCE

CS

SCK

01234567

SI

00000110

High-impedance

SO

FIGURE 3-5:

WRITE DISABLE SEQUENCE

CS

SCK

01234567

SI

0 0 0 0 0 1 10 0

High-impedance

SO

© 2006 Microchip Technology Inc.

DS21204E-page 9

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