KBD43W13 데이터 시트보기 (PDF) - SMSC -> Microchip
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KBD43W13 Datasheet PDF : 22 Pages
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AC TIMING
NO.
DESCRIPTION
MIN. MAX. UNIT
T1
Address Setup Time from WRB
0
nS
T2
Address Setup Time from RDB
0
nS
T3
WRB Strobe Width
20
nS
T4
RDB Strobe Width
20
nS
T5
Address Hold Time from WRB
0
nS
T6
Address Hold Time from RDB
0
nS
T7
Data Setup Time
50
nS
T8
Data Hold Time
0
nS
T9
Gate Delay Time from WRB
10
30
nS
T10
RDB to Drive Data Delay
40
nS
T11
RDB to Floating Data Delay
0
20
nS
T12
Data Valid After Clock Falling (SEND)
4
µS
T13
K/B Clock Period
20
µS
T14
K/B Clock Pulse Width
10
µS
T15
Data Valid Before Clock Falling (RECEIVE)
4
µS
T16
K/B ACK After Finish Receiving
20
µS
T17
RC Fast Reset Pulse Delay (8 MHz)
2
3
µS
T18
RC Pulse Width (8 MHz)
6
µS
T19
Transmit Timeout
2
mS
T20
Data Valid Hold Time
0
µS
T21
X1/X2 Period (6−12 MHz)
83 167
nS
T22
Duration of CLK inactive
30
50
µS
T23
Duration of CLK active
30
50
µS
T24
Time from inactive CLK transition, used to time when 5
25
µS
the auxiliary device sample DATA
T25
Time of inhibit mode
100 300
µS
T26
Time from rising edge of CLK to DATA transition
5 T28-5
µS
T27
Duration of CLK inactive
30
50
µS
T28
Duration of CLK active
30
50
µS
T29
Time from DATA transition to falling edge of CLK
5
25
µS
T30
Mode detect signal after P10 goes high
Typical 1 mS
T31
High pulse of mode detect signal
Typical 220 µS
T32
Low pulse of mode detect signal
Typical 220 µS
T33
Mode detect signal after RESET goes high
Typical 1 mS
T34
Time out of AT mode‘ s mode detect signal
Typical 64 mS
14
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