COM20022I 데이터 시트보기 (PDF) - SMSC -> Microchip

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COM20022I

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

The following rough timing diagram of the non-burst mode DMA data transfer is included for illustration

purposes.

DREQ

nDACK

Read/Write

Signal

TC

FIGURE 6 - NON-BURST MODE DMA DATA TRANSFER ROUGH TIMING

The timing of the Burst mode DMA data transfer

is found in the Timing Diagrams section of this

data sheet. The basic sequence of operation is

as follows:

!" nDACK becomes active (low) upon DREQ

becoming active (high) and catching the

host bus (AEN= “1”).

!" DREQ becomes inactive after TC asserts

(when nDACK= “0”). In this case, DREQ

doesn't become active again after nDACK

becomes inactive.

!" nDACK becomes inactive after DREQ= 0

and the present cycle finishes.

The following rough timing diagram of the non-

burst mode DMA data transfer is included for

illustration purposes.

DREQ

nDACK

Read/Write

Signal

TC

FIGURE 7 - BURST MODE DMA DATA TRANSFER ROUGH TIMING

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