FS6108-01 데이터 시트보기 (PDF) - AMI Semiconductor
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FS6108-01 Datasheet PDF : 5 Pages
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FS6108-01
1:9 Zero Delay Buffer IC
1.0 Features
• Generates up to nine clock outputs, grouped as 4-4-1
from one reference clock input
• Pin enable/disable of two banks of four clocks
• Auto power-down shuts off PLL, brings outputs low in
the absence of any REF input
• Tracking skew < 200ps (spread-spectrum tolerant)
• Input-to-output propagation delay < 200ps
• Available in a 16-pin 0.150” SOIC
Table 1: Clock Enable Configuration
Figure 1: Block Diagram
REF
S2
S1
PLL
Control
CONTROL
S2
S1
0
0
0
1
1
0
1
1
CLOCK OUTPUTS (MHz)
CLK_A1:4 CLK_B1:4 CLK_FB
Tristate
Driven
Driven
Driven
Tristate
Tristate
Driven
Driven
Driven
Driven
Driven
Driven
Source
PLL
PLL
REF
PLL
FS6108
VDD
CLK_FB
CLK_A1
CLK_A2
CLK_A3
CLK_A4
VSS
VDD
CLK_B1
CLK_B2
CLK_B3
CLK_B4
VSS
Table 2: Pin Descriptions
Key: DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down;
DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN TYPE
2
DOD
3
DOD
14
DOD
15
DOD
6
DOD
7
DOD
10
DOD
11
DOD
16
DOD
1
DID
8, 9
DIU
4, 13
P
5, 12
P
NAME
CLK_A1
CLK_A2
CLK_A3
CLK_A4
CLK_B1
CLK_B2
CLK_B3
CLK_B4
CLK_FB
REF
S2, S1
VDD
VSS
DESCRIPTION
Clock output
Clock output
Clock output
Bank A
Clock output
Clock output
Clock output
Clock output
Bank B
Clock output
Clock output that also provides an in-
ternal feedback connection to the PLL
Reference clock input
Two select inputs that enable and dis-
able the clock outputs, and enable or
bypass the PLL
3.3V power supply
Ground
Figure 2: Pin Configuration
REF 1
CLK_A1 2
CLK_A2 3
VDD 4
VSS 5
CLK_B1 6
CLK_B2 7
S2 8
16 CLK_FB
15 CLK_A4
14 CLK_A3
13 VDD
12 VSS
11 CLK_B4
10 CLK_B3
9 S1
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ISO9001
3.4.02
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