![](/html/Hitachi/142866/page11.png)
8. INTERFACE TIMING CHART
8.1 TIMING CHART
CL1
CL2
Dummy data
UD7
RB
Y1 Y9
UD6
GR
Y2 Y10
UD1
RB
Y7 Y15
UD0
Dummy data
GR
Y8 Y16
LD7
RB
Y1921 Y1929
LD6
GR
Y1922 Y1930
LD1
RB
Y1927 Y1935
LD0
GR
Y1928 Y1936
X1
X241
FLM
(Reduction)
CL1
FLM
(240+n) × T
G
Y1913
B
Y1914
G
Y1919
B
Y1920
G
Y1913
B
Y1914
G
Y1919
B
Y1920
X2
X242
Note(1)
UD0~UD7
X1 X2
Y239 Y240 Dummy data
LD0~LD7
X241 X242
Y479 Y480 Dummy data
Note(1) : The interval of CL1 pulse must be same including the vertical blanking period.
Dis p l a ys ,
Hitachi, Ltd. Date
Nov. 4, '99
Sh. 3284PS 2708 - SX21V001-Z4 - 4
No.
Page 8-1/7