PBL38772 데이터 시트보기 (PDF) - Ericsson

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PBL38772

Subscriber Line Interface Circuit (SLIC)

Ericsson  

PBL 387 72

Parameter

Four-wire to longitudinal balance, BFLE

BFLE = 20 × Log

ERX

VLo

Two-wire return loss, r

r = 20 × Log |ZTRX + ZL|

|ZTRX – ZL|

TIPX idle voltage, VTI

RINGX idle voltage, VRI

Open loop voltage, |VTR Open|

Ref

fig Conditions

4 active state

0.2 kHz < f < 3.4 kHz

0.2 kHz < f < 0.5 kHz

0.5 kHz < f < 1.0 kHz

1.0 kHz < f < 3.4 kHz, Note 3

active normal, IL = 0

active normal, IL = 0

active, IL = 0

Four-wire transmit port (VTX)

Overload level, VTXO

Off-hook, IL ≥ 10mA

On-hook, IL ≤ 5mA

Output offset voltage, ∆VTX

Output impedance, ZTX

5

Load impedance > 20 kΩ,

Load impedance > 20 kΩ,

1% THD, Note 4

0.2 kHz < f < 3.4 kHz

Four-wire receive port (receive summing node = RSN)

RSN dc offset voltage, VRSNdc

IRSN = 0 mA

RSN impedance

0.2 kHz < f < 3.4 kHz

RSN current, IRSN, to metallic loop

current ,IL, gain, αRSN

0.3 kHz < f < 3.4 kHz

Min

Typ

Max

Unit

40

58

dB

25

dB

27

dB

23

dB

- 0.9

V

- 51

V

43

50

56

V

0.5

0.5

-100

VPeak

VPeak

100

mV

5

20

Ω

-25

25

mV

10

50

Ω

400

ratio

C

RLT

VLo

RLR

TIPX

VTX

VTR PBL 387 72

RT

E RX

RINGX RSN

RRX

1

ωC

<<

150Ω,

RLT

= RLR = 300Ω

RT = 120kΩ,

RRX = 120kΩ

Figure 4. Metallic to longitudinal, BMLE and four-wire to longitudinal balance, BFLE.

C

RL

TIPX

VTX

1

ωC

<<

RL

,

RL

=

600Ω

ILdc

PBL 387 72

RT

VTXO

RT = 120kΩ,

RRX = 120kΩ

EL

RINGX RSN

RRX

Figure 5. Overload level, VTXO, four-wire transmit port.

4

EN/LZT 146 136 R1A © Ericsson Microelectronics, December 2001

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