ST7529 데이터 시트보기 (PDF) - Unspecified

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ST7529

32-Gray Scale Dot Matrix LCD Controller / Driver

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ST7529

7.3 DISPLAY DATA RAM (DDRAM)

7.3.1 DDRAM

It is 160 X 255 X 5 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the LINE

address and column address. Since the display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels,

data transfer related restrictions are reduced, and the display would be flexible.

The RAM on ST7529 is separated to a block per 4 lines to allow the display system to process data on the block basis.

The reading and writing RAM operations of MPU are performed via the I/O buffer circuit. Reading of the RAM for the liquid

crystal drive is controlled from another separate circuit.

Refer to the following memory map for the RAM configuration.

Ver 1.8

21/86

2007/10/25

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