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NXP Semiconductors
PN544
Near field communication (NFC) controller
3. Features
Low power HT80C51 MX CPU core with 72 KBytes ROM, 44 KBytes non-volatile
memory for code, 8 KBytes non-volatile memory for data and 4 KBytes RAM
Buffered output drivers to connect an NFC antenna with minimum number of external
components
Integrated configurable Polling Loop for automatic device discovery
Integrated data mode detector for automatic anticollision
Integrated non-volatile memory to store data and executable code for customization
Flexible clock supply concept to facilitate PN544 integration
Integrated FracNPLL to make use of cellular reference clock
27.12 MHz direct clock input to minimize current consumption (integrated
FracNPLL disabled)
Internal oscillator to connect an 27.12 MHz crystal (in case of absent reference
clock, then FracNPLL is disabled to minimize current consumption)
Flexible power supply concept to facilitate PN544 integration
Integrated power management unit to be directly connected to a mobile battery
2.3 to 5.5 V power supply
Fully configurable power behavior
Supporting various power saving modes per embedded firmware
Automatic host wake up via host control interface interfaces when PN544 is in
Standby power saving mode
Integrated self test to test external antenna matching circuit
Highly integrated analog circuitry to modulate, demodulate, encode requests and
decode responses
Integrated RF Level detector
Typical operating distance in PCD mode for communication to a ISO 14443A/Mifare,
ISO14443B, NFC-IP1 passive target or FeliCa card up to 50 mm depending on the
antenna size and tuning and power supply
Typical operating distance in VCD mode for communication to a ISO/IEC
15693/ICODE TAG more than 50 mm depending on the antenna size and tuning,
power supply and form factor of the TAG
Typical operating distance in ISO14443A/Mifare, ISO14443B, Type B’ or FeliCa card
emulation mode of about 100 mm depending on the antenna size and tuning and the
external field strength
Supports Mifare Classic encryption in reader/writer mode
Various host control interfaces
SPI interface
I2C interface
High Speed Asynchronous Serial UART
Various interfaces to secure companion chip
NFC-WI according to ECMA 373 standard
SWP
Flexible interrupts using IRQ pin
Power switch for secure companion chip
Freely programmable general purpose IO ports
134812
Objective short data sheet
Rev. 1.2 — 4 September 2007
© NXP B.V. 2007. All rights reserved.
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