MT6572 데이터 시트보기 (PDF) - Unspecified

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MT6572

Mediatek / Dual-core platform with HSPA+

Unspecified 

5

4

3

2

1

BPI0~4 and 10~11 are 2G+3G mode both

U101-A

BPI5~9 and 12~14 are 3G mode only

[6] RX_I_P

D2 DL_I_P

BPI_BUS0 B12

ASM_VCTRL_A [6]

[6] RX_I_N

C2 DL_I_N

BPI_BUS1 B11

ASM_VCTRL_B [6]

[6] RX_Q_P

[6] RX_Q_N

B1 DL_Q_P

C1 DL_Q_N

BPI_BUS2 C12

BPI_BUS3 A11

ASM_VCTRL_C [6]

WG_GGE_PA_ENABLE

[6]

U101-D

BPI_BUS4 D11

[3] AUD_MISO

J1 AUD_DAT_MISO

[6] TX_I_P

A2 UL_I_P

BPI_BUS5 C11

[3] AUD_CLK

K5 AUD_CLK_MOSI

[6] TX_I_N

B2 UL_I_N

BPI_BUS6 A13

GPIO137_GPS_LNA_EN [10]

[3] AUD_MOSI

K1 AUD_DAT_MOSI

[6] TX_Q_P

B4 UL_Q_P

D

[6] TX_Q_N

B3 UL_Q_N

BPI_BUS7 A10

W_PA_B1_EN

BPI_BUS8 B10

[3] PMIC_SPI_MOSI

[3] PMIC_SPI_MISO

L2 PMIC_SPI_MOSI

L5 PMIC_SPI_MISO

reserve for JTAG debug

D

BPI_BUS9 D10

BPI_BUS10 E9

W_PA_B8_EN

[3,4]PMIC_SPI_CS

[3] PMIC_SPI_SCK

L4 PMIC_SPI_SCK

K2 PMIC_SPI_CSN

VIO18_PMU

BPI_BUS11 E8

BPI_BUS12 B9

EINT7_MAG [80]

[3] WATCHDOG

G2 WATCHDOG

[3] SIM1_SCLK

R208 NC

VM0

A8 VM0

BPI_BUS13 B8

VM1

A7 VM1

BPI_BUS14 E7

BPI_BUS15 D7

EINT4_GY [80]

EINT5_ALP

[21]

R210=20K,DDR1,VM=1.8V;

R210=NC,DDR2,VM=1.2V

[3,6]SRCLKENA

R210

NC

[3] EINT_PMIC

H4 SRCLKENA

J2 EINTX

[6] TXBPI

[6] WG_GGE_PA_VRAMP

D5 TXBPI

F2 APC

F3 VBIAS

BSI_DATA2 D6

BSI_DATA1 C7

BSI_DATA0 F9

BSI_EN F11

BSI_CLK G11

BSI-A_DAT2 [6]

BSI-A_DAT1 [6]

BSI-A_DAT0 [6]

BSI-A_EN [6]

BSI-A_CK [6]

[3] SIM1_SCLK

[3] SIM1_SIO

[3] SIM2_SCLK

[3] SIM2_SIO

H5 SIM1_SCLK

M3 SIM1_SIO

J5 SIM2_SCLK

M1 SIM2_SIO

Normal : NC

JTAG : 20K

Reserve R footprint

for JTAG debugging

MT6572/TMP/SMD

MT6572/TMP/SMD

U101-E

C

[6] CLK1_BB

E1 CLK26M

SYSTEM PWM

PWM_A D12

PWM_B E12

GPIO128_PWM_BL_CTRL

C

[3] CLK32K_BB

H2 CLK32K_IN

[3] RESETB

M2 SYSRSTB

LCD

Parallel

LPD17 N1

LPD16 N2

EINT6_HP [5]

G4 TESTMODE

LPD15 N3

AC24 FSOURCE

LPD14 P2

LPD13 N4

R216 R219 R220

LPD12 R2

1 TP203

[3] CHD_DP

[3] CHD_DM

J26 CHD_DP

J25 CHD_DM

BC 1.1

LPD11 N5

LPD10 R1

LPD9 P5

MC1INS [2]

NC

NC

NC

Based on your system level design , if better

LPD8 T1

[13] GPIO_CMPDN2

[13] GPIO_CMRST2

[13] CMPDN

U101-G

L25 CMPDN2

K25 CMRST2

H22 CMPDN

desense performance is needed on your

system , please refer to desense

pMeIPrI_fo2nrdm_CaAnMce enhance proposal

Parallel 8-bit

R209

NC

[14] USB_DM

[14] USB_DP

90-ohm differential

R203

USB_VRT

close to BB

[13] SCL_0

[13] SDA_0

G26 USB_DM

G25 USB_DP

H25 USB_VRT

USB 2.0

C25 SCL_0

i2C

C26 SDA_0

LPD7 R5

LPD6 T2

LPD5 T5

LPD4 U2

LPD3 T3

LPD2 U5

LPD1 T4

LPD0 V2

R221 R222 R223

[13] CMRST

J22 CMRST

[12,21]SCL_1

B24 SCL_1

CMMCLK Y22

CMMCLK [13]

[12,21]SDA_1

B23 SDA_1

NC

NC

NC

2 MIPI_RDN0

2 MIPI_RDP0

R24

R23

RDN0

RDP0

MIPI_CAM

CMPCLK Y23

CMPCLK

[13]

LPCE0B AD25

2 MIPI_RDN1

2 MIPI_RDP1

R22 RDN1

R21 RDP1

RCN_A V25

CMVSYNC

[13]

GPIO100_CTP_RSTB

GPIO99_FLASH_EN

F24 SPI_MISO

F25 SPI_MOSI

SPI

LPTE AB26

LRSTB AC26

LPTE [12]

GPIO_LRSTB [12]

2

MIPI_RCN

R26 RCN

RCP_A W25

CMHREF

[13]

GPIO98_FLASH_SEL

F23 SPI_SCK

LPRDB AA22

2

MIPI_RCP

T26 RCP

RDN1_A V24

CMDAT7

[13]

[12] EINT3_CTP

E23 SPI_CS

LPA0 AB23

RDP1_A V23

CMDAT6

[13]

LPWRB AC25

2 MIPI_TDN0

2 MIPI_TDP0

P19 TDN0

P20 TDP0

MIPI_LCD

RDN0_A U22

RDP0_A U21

CMDAT5

CMDAT4

[13]

[13]

2 MIPI_TDN1

2 MIPI_TDP1

N25 TDN1

N26 TDP1

P23 TDN2

CMDAT3 Y26

CMDAT2 Y25

CMDAT3

CMDAT2

[18] MC1CMD

[18] MC1CK

[18] MC1DAT0

K23 MC1_CMD

L21 MC1_CK

T-flash

KP

K22 MC1_DAT0

KROW0 B25

KROW1 A24

KROW2 B26

KROW0 [20]

KROW1 [20]

JTMS

TP205

P24 TDP2

CMDAT1 AA25

CMDAT1

[18] MC1DAT1

M22 MC1_DAT1

KCOL0 C24

KCOL0 [20]

B

2 MIPI_TCN

N20 TCN

CMDAT0 AB25

CMDAT0

2 MIPI_TCP

N19 TCP

[18] MC1DAT2

[18] MC1DAT3

M25 MC1_DAT2

L26 MC1_DAT3

KCOL1 D24

KCOL2 A25

KCOL1 [20]

TP206

B

GPIO109_SPK_EN

R202

MIPI_VRT P26 VRT

R202 close to BB

MT6572/TMP/SMD

GPIO99_FLASH_EN

GPIO98_FLASH_SEL

R212

R213

LCD_ID

C201

B7 AUX_IN0

B6 AUX_IN1

ADC

C5 AUX_IN2_XP

B5 AUX_IN3_YP

C4 AUX_IN4_XM

A5 AUX_IN5_YM

UART

UTXD1 E25

URXD1 D25

UTXD2 E26

URXD2 F26

MT6572/TMP/SMD

UTXD1

URXD1

UTXD2

URXD2

1 TP201

1 TP202

1 TP207 TP209

MT6572 support JTAG from below :

1. KP (recommand)

2. MC1

3. CAM

for JTAG pin out from MC1/CAM, refer

to HW design notice

VIO18_PMU

R211

R217 NC

R218 NC

R214 NC

EINT5_ALP

EINT7_MAG

EINT4_GY

EINT6_HP

[21]

[80]

[80]

[5]

A

VCAMD_IO_PMU

[13] SCL_0

[13] SDA_0

R204 R205

Power by CAM_IO

VIO18_PMU

MAINBOARD MARK

TP212

1

TP214

1

TP213

1

TP211

1

A

R206 R207

[12,21]SCL_1

[12,21]SDA_1

Power by CTP, MEMS sensor

ÉîÛÚÊнðÁ¢Í¨ÐÅÉ豸ÓÐÏÞ¹«Ë¾

Title

WBW5210

Size

Document Number

Rev

D

02 BB Peripheral

?

Date:

Friday, February 14, 2014

Sheet

3

of

17

5

4

3

2

1

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