FM25C160B 데이터 시트보기 (PDF) - Unspecified

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FM25C160B

16Kb Serial 5V F-RAM Memory

Unspecified 

FM25C160B - 16Kb 5V SPI F-RAM

Figure 9. Memory Write

Figure 10. Memory Read

Endurance

Internally, a F-RAM operates with a read and restore

mechanism. Therefore, endurance cycles are applied

for each access: read or write. The F-RAM

architecture is based on an array of rows and

columns. Each access causes a cycle for an entire

row. In the FM25C160B, a row is 64 bits wide.

Every 8-byte boundary marks the beginning of a new

row. Endurance can be optimized by ensuring

frequently accessed data is located in different rows.

Regardless, F-RAM read and write endurance is

effectively unlimited at the 20MHz clock speed.

Even at 2000 accesses per second to the same row, 15

years time will elapse before 1012 endurance cycles

occur.

Rev. 3.0

Jan. 2012

Page 8 of 13

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