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AD6657 Datasheet PDF : 32 Pages
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AD6657
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
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4
5
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10
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12
A AGND VIN+C VIN–C AGND AVDD CLK– CLK+ AVDD AGND VIN–B VIN+B AGND
B AGND AGND VCMC AGND AVDD AVDD AVDD AVDD AGND VCMB AGND AGND
C VIN+D AGND AGND CSB SDIO SCLK PDWN SYNC MODE AGND AGND VIN+A
D VIN–D VCMD AGND AVDD AVDD AVDD AVDD AVDD AVDD AGND VCMA VIN–A
E AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND
F AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
G DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND
H DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD
J D0–CD D2–CD D4–CD D6–CD D8–CD D10–CD D0–AB D2–AB D4–AB D6–AB D8–AB D10–AB
K D0+CD D2+CD D4+CD D6+CD D8+CD D10+CD D0+AB D2+AB D4+AB D6+AB D8+AB D10+AB
L D1–CD D3–CD D5–CD D7–CD D9–CD DCO–CD D1–AB D3–AB D5–AB D7–AB D9–AB DCO–AB
M D1+CD D3+CD D5+CD D7+CD D9+CD DCO+CD D1+AB D3+AB D5+AB D7+AB D9+AB DCO+AB
Figure 4. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
A5, A8, B5, B6, B7, B8,
D4, D5, D6, D7, D8,
D9, E2, E3, E4, E5, E6,
E7, E8, E9, E10, E11
AVDD
A1, A4, A9, A12, B1,
B2, B4, B9, B11, B12,
C2, C3, C10, C11, D3,
D10, E1, E12, F1, F2,
F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12
AGND
H1, H2, H3, H4, H5,
H6, H7, H8, H9, H10,
H11, H12
DRVDD
G1, G2, G3, G4, G5,
G6, G7, G8, G9, G10,
G11, G12
DRGND
A7
CLK+
A6
CLK−
C12
VIN+A
D12
VIN−A
D11
VCMA
A11
VIN+B
A10
VIN−B
B10
VCMB
A2
VIN+C
A3
VIN−C
B3
VCMC
C1
VIN+D
D1
VIN−D
D2
VCMD
K7
D0+AB
J7
D0−AB
Type
Supply
Ground
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Output
Description
Analog Power Supply (1.8 V Nominal)
Analog Ground
Digital Output Driver Supply (1.8 V Nominal)
Digital Output Driver Ground
ADC Clock Input—True
ADC Clock Input—Complement
Differential Analog Input Pin (+) for Channel A
Differential Analog Input Pin (−) for Channel A
Common-Mode Level Bias Output for Analog Input Channel A
Differential Analog Input Pin (+) for Channel B
Differential Analog Input Pin (−) for Channel B
Common-Mode Level Bias Output for Analog Input Channel B
Differential Analog Input Pin (+) for Channel C
Differential Analog Input Pin (−) for Channel C
Common-Mode Level Bias Output for Analog Input Channel C
Differential Analog Input Pin (+) for Channel D
Differential Analog Input Pin (−) for Channel D
Common-Mode Level Bias Output for Analog Input Channel D
Channel A and Channel B LVDS Output Data 0—True
Channel A and Channel B LVDS Output Data 0—Complement
Rev. B | Page 10 of 32
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