![](/html/NXP/140437/page17.png)
NXP Semiconductors
PCA9557
8-bit I2C-bus and SMBus I/O port with reset
SDA
tBUF
SCL
tr
tLOW
tHD;STA
P
S
tHD;DAT
tf
tHIGH
tSU;DAT
Fig 21. Definition of timing on the I2C-bus
tHD;STA
tSP
tSU;STA
Sr
tSU;STO
P
002aaa986
START
SCL
ACK or read cycle
SDA
30 %
RESET 50 %
IOn
trec(rst)
Fig 22. Definition of RESET timing
trst
50 %
tw(rst)
50 %
trst
50 %
I/O configured
as inputs
002aad289
PCA9557
Product data sheet
Rev. 06 — 11 June 2008
© NXP B.V. 2008. All rights reserved.
17 of 26