D16750 데이터 시트보기 (PDF) - Unspecified

부품명

상세내역

일치하는 목록

D16750

Configurable UART with FIFO

Unspecified 

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ Encrypted, or plain text EDIF netlist

♦ VHDL & VERILOG test bench

environment

◊ Active-HDL automatic simulation macros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, minor

and major versions changes

● Delivery the documentation updates

● Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty per chip fees make

using of IP Core easy and simply.

Single Site license option is dedicated for

small and middle sized companies making its

business in one place.

Multi Sites license option is dedicated for

corporate customers making its business in

several places. Licensed product can be used

in selected branches of corporate.

In all cases number of IP Core instantiations

within a project, and number of manufactured

chips are unlimited. The license is royalty per

chip free. There is no time of use restrictions.

There are two formats of delivered IP Core

● VHDL, Verilog RTL synthesizable source

code called HDL Source

● FPGA EDIF/NGO/NGD/QXP/VQM called

Netlist

CONFIGURATION

The following parameters of the D16550 core

can be easy adjusted to requirements of

dedicated application and technology.

Configuration of the core can be prepared by

effortless changing appropriate constants in

package file. There is no need to change any

parts of the code.

• Baud generator

- enable

- disable

• External RCLK source

- enable

- disable

• External BAUDCLK source

- enable

- disable

• Modem Control logic

- enable

- disable

• SCR Register

- enable

- disable

• FIFO Control logic

- enable

- disable

APPLICATION

addr

CPU ale

addr

latch

datao(7:0)

datai(7:0)

we

rd

cs

int

addr(2:0)

D16550

clk

rst

baudclk

rclk

datai(7:0)

so

datao(7:0)

si

wr

rts

rd

dtr

cs

dsr

intr

dcd

cts

rxrdy

ri

txrdy

out1 baudclken

out2

rclken

EIA

Drivers

Typical D16550 and processor connection is

shown in figure above.

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2009 DCD – Digital Core Design. All Rights Reserved.

Share Link: