AD7912 데이터 시트보기 (PDF) - Analog Devices
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AD7912 Datasheet PDF : 32 Pages
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AD7912/AD7922
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
the Timing Specifications section.
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput
is 1 MSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 1 µs
With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7922 can also operate with slower clock frequencies. As
shown in Figure 7, when fSCLK = 5 MHz and the throughput rate
is 315 kSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 3.17 µs
With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum tQUIET between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
CS
SCLK
tCONVERT
t2
t6
1
2
3
4
5
DOUT
t3
Z ZERO
THREE-STATE
DIN
X
X
t4
CHN MOD DB11
t8
t9
CHN STY
X
t7
DB10
X
t1
B
13
14
t5
DB2 DB1
15
DB0
16
t10
tQUIET
THREE-STATE
X
X
X
Figure 6. AD7922 Serial Interface Timing Diagram
CS
SCLK
t2
tCONVERT
1
2
3
4
5
12.5(1/fSCLK)
B
13
14
C
15
t10
16
tACQUISITION
tQUIET
1/THROUGHPUT
Figure 7. Serial Interface Timing Example
Rev. 0 | Page 8 of 32
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