P4C188L-35JC 데이터 시트보기 (PDF) - Performance Semiconductor
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P4C188L-35JC Datasheet PDF : 8 Pages
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P4C188/188L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)
ADDRESS
CE
WE
DATA IN
(11)
t WC
t AS
t CW
t AW
t WP
t AH
t WR
t DW
t DH
DATA VALID
DATA OUT
HIGH IMPEDANCE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
TRUTH TABLE
Mode
CE
WE
Standby H
X
Read
L
H
Write
L
L
Output
High Z
D
OUT
D
IN
Power
Standby
Active
Active
DOUT
255Ω
+5V
480Ω
30pF**(5pF* for tHHZZ,,tLt ZL,Z ,
ttWWZZanadndtOWtO)W )
D OUT
RTH = 166.5 Ω
VTH = 1.73 V
30pF* (5pF* for t HZ , t LZ ,
t WZ and tOW )
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C188/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
Figure 2. Thevenin Equivalent
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
68
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