SK100EL14W(2001) 데이터 시트보기 (PDF) - Semtech Corporation
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SK100EL14W Datasheet PDF : 4 Pages
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HIGH-PER.ORMANCE PRODUCTS
Description
SK10/100EL14W
1:5 Clock Distribution Chip
.eatures
The SK10/100EL14W is a 1:5 Clock Distribution Chip
designed specifically for low skew clock distribution
applications. This device is fully compatible with
MC100EL14 and MC100LVEL14.
The device can be driven by either differential or single-
ended ECL/PECL input signals. The SK10/100EL14W
provides a VBB output for either single-ended use or DC
bias for AC coupling to the device. VBB is an output pin
and should be used as a bias for the EL14W as its current
sink/source capability is limited. Whenever used, VBB
should be bypassed to VCC via a 0.01 µF capacitor.
The EL14W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pulldown resistor) the
SEL pin will select the differential clock input. The Common
Enable pin (EN*) is synchronous so that the outputs will
only be enabled/disabled when they are already in the
LOW state. This avoids the chance of generating a runt
clock pulse when the device is enabled/disabled as can
happen with an asynchronous control. The internal flip-
flops are clocked on the falling edge of the input clock;
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
.unctional Block Diagram
• Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)
• High Bandwidth Output Transition
• Max. 50 ps Output-to-Output Skew (Typ. 30 ps)
• VBB Output
• Synchronous Enable/Disable
• Multiplexed Clock Input
• 75 KΩ Internal Input Pulldown Resistors
• New Differential Input Common Mode Range
• Fully Compatible with MC100EL14 and
MC100LVEL14
• ESD Protection of >4000 V
• Industrial Temperature Range: –40oC to +85oC
• Available in 20-Pin SOIC (150 mils) Package
Pin Descriptions
Pin
.unction
CLK, CLK*
Differential Clock Inputs
SCLK
Scan Clock Input
EN*
Sync Enable
SEL
Clock Select Input
VBB
Reference Output Voltage
Q0-Q4, Q0*-Q4* Differential Clock Outputs
Q0 1
Q0* 2
Q1 3
Q1* 4
Q2 5
Q2* 6
Q3 7
Q3* 8
Q4 9
Q4* 10
QD
1
0
20 VCC
19 EN*
18 VCC
17 NC
16 SCLK
15 CLK
14 CLK*
13 VBB
12 SEL
11 VEE
Function Table
CLK
SCLK
SEL
EN*
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
* On next negative transition of CLK or SCLK
Revision 1/February 12, 2001
1
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