UT06MRA500 데이터 시트보기 (PDF) - Aeroflex UTMC

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UT06MRA500

UT0.6µCRH Commercial RadHard™ Gate Array Family

Aeroflex UTMC 

ASIC DESIGN SOFTWARE

Using a combination of state-of-the-art third-party and

proprietary design tools, Aeroflex delivers the CAE support

and capability to handle complex, high-performance ASIC

designs from design concept through design verification and

test.

Aeroflex’s flexible circuit creation methodology supports high

level design by providing UT0.6CRH libraries for Mentor

Graphics and Synopsys synthesis tools. Design verification is

performed in any VHDL or Verilog simulator or the Mentor

Graphics environment, using Aeroflex’s robust libraries.

Aeroflex also supports Automatic Test Program Generation to

improve design testing.

Aeroflex HDL DESIGN SYSTEM

Aeroflex offers a Hardware Description Language (HDL)

design system supporting VHDL and Verilog. Both the VHDL

and Verilog libraries provide sign-off quality models and

robust tools.

High Level Design Activities

Synopsys

VSS/VCS

HDL Tool

Supplier

Mentor

ModelSim

Cadence

NSIM

Verilog XL

Aeroflex HDL

Design System

VCS

Aeroflex

Gaisler IP

Completed

ASIC Design

Aeroflex HDL Design Flow

The VHDL libraries are VITAL 3.0 compliant, and the Verilog

libraries are OVI 1.0 compliant.With the library capabilities

Aeroflex provides, you can use High Level Design methods to

synthesize your design for simulation. Aeroflex also provides

tools to verify that your HDL design will result in working

ASIC devices.

Aeroflex’s HDL design system lets you easily access

Aeroflex’s RadHard capabilities.

ADVANTAGES OF THE AEROFLEX HDL DESIGN

SYSTEM

• The Aeroflex HDL Design System gives you the freedom

to use tools from Synopsys, Mentor Graphics, Cadence,

and other vendors to help you synthesize and verify a

design.

• Aeroflex’s Logic Rules Checker and Tester Rules Checker

allow you to verify partial or complete designs for

compliance with Aeroflex design rules.

• Aeroflex HDL Design System accepts back-annotation of

timing information through SDF.

• Your design stays entirely within the language in which

you started (VHDL or Verilog) preventing conversion

headaches.

XDTsm (eXternal Design Translation)

Through Aeroflex’s XDT services, customers can convert an

existing non-Aeroflex design to Aeroflex’s processes. The

XDT tool is particularly useful for converting an FPGA to an

Aeroflex radiation-tolerant gate array. The XDT translation

tools convert industry standard netlist formats and vendor

libraries to Aeroflex formats and libraries. Industry standard

netlist formats supported by Aeroflex include:

• VHDL

• Verilog HDLTM

• FPGA source files (Actel, Altera, Xilinx)

• EDIF

• Third-party netlists supported by Synopsys

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