NT6881 데이터 시트보기 (PDF) - Novatek Microelectronics

부품명

상세내역

일치하는 목록

NT6881

USB Keyboard Micro-Controller

Novatek Microelectronics 

NT68P81

3. OTP ROM: 6K X 8 bits

The built-in OTP ROM program code, executed by the 6502 CPU, has a capacity of 6K x 8-bit and is addressed from

E800H to FFFFH. It can be programmed by the universal EPROM writer through a conversion adapter and programming

configuration such as INTEL - 27C64. In the OPERATING mode, the OTP ROM is integrated with the system and it cannot

be directly accessed. When the user wants to work with the OTP ROM alone, the user must first enter the

PROGRAMMING mode by setting: PIN < RESET = VPP>. At this time, through multiplex pins, we can use familiar

procedures to program and verify the OTP ROM block with the universal programmer.

OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)

(VDD = 5V, TA = 25℃, unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

VIH

Input Voltage

VDD - 0.3

VIL

-0.3

IIL

Input Current

IOH

Output Voltage

-400

IOL

1

IDD

Operating Current

ISTB1

Standby Current

Note:

1. All inputs and outputs are CMOS compatible

2. F = 3MHz, lout = 0mA, CE = VIH. VDD = 5V

3. CE = VIH, OE = VIL, VDD = 5V

VDD + 0.3

V

0.3

V

+/-10

µA

µA

mA

1

mA

100

µA

Test Conditions

Note

1

1

VDD = 5V, VOH = 4.5V

VDD = 5V, VOL = 0.5V

F = 3MHz

2

3

OTP ROM Mega Cell A.C. Electrical Characteristics (READ Mode)

(VDD = 5V, TA = 25℃, unless otherwise specified)

Symbol

Parameter

Min.

Max.

Unit

Tcyc

Cycle Time

250

ns

T12

Non-overlap Time to PH1 & PH2

5

65

ns

Tacc

Address Access Time

145

ns

Tce

OTPCE to Output Valid

145

ns

Tst

Output Data Setup Time

20

ns

Toh

Output Data Hold Time

0

ns

Conditions

4.5V < VDD < 5.5V

OTP ROM Mega Cell A.C. Test Conditions

Output Load

Input Pulse Rise and Fall Times

Input Pulse Levels

Timing Measurement Reference Level

1 CMOS Gate and CL = 10pF

10ns Max.

0V to 5V

Inputs 0V and 5V Outputs 0.3V and 4.7V

8

Share Link: