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MC74AC190D Datasheet PDF : 8 Pages
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MC74AC190
FUNCTIONAL DESCRIPTION
The MC74AC190 is a synchronous up/down BCD decade
counter. It contains four edge-triggered flip-flops with internal
gating and steering logic to provide individual preset, count-up
and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information present
on the Parallel Load inputs (P0–P3) is loaded into the counter
and appears on the Q outputs. This operation overrides the
counting functions, as indicated in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When CE
is LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction of
counting is determined by the U/D input signal, as indicated in
the Mode Select Table. CE and U/D can be changed with the
clock in either state, provided only that the recommended
setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The terminal count (TC) output is normally LOW. It
goes HIGH when the circuits reach zero in the count down
mode or 9 in the count up mode. The TC output will then
remain HIGH until a state change occurs, whether by counting
or presetting or until U/D is changed. The TC output should not
be used as a clock signal because it is subject to decoding
spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When CE
is LOW and TC is HIGH, RC output will go LOW when the clock
next goes LOW and will stay LOW until the clock goes HIGH
again. This feature simplifies the design of multistage
counters, as indicated in Figures a and b. In Figure a, each RC
output is used as the clock input for the next higher stage. This
configuration is particularly advantageous when the clock
source has a limited drive capability, since it drives only the first
stage. To prevent counting in all stages it is only necessary to
inhibit the first stage, since a HIGH signal on CE inhibits the
RC output pulse, as indicated in the RC Truth Table. A
disadvantage of this configuration, in some applications, is the
timing skew between state changes in the first and lost stages.
This represents the cumulative delay of the clock as it ripples
through the preceding stages.
A method of causing state changes to occur simultaneously
in all stages is shown in Figure b. All clock inputs are driven in
parallel and the RC outputs propagate the carry/borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the
negative-going edge of the carry/borrow signal to ripple
through to the last stage before the clock goes HIGH. There
is no such restriction on the HIGH state duration of the clock,
since the RC output of any device goes HIGH shortly after its
CP input goes HIGH.
The configuration shown in Figure c avoids ripple delays
and their associated restrictions. The CE input for a given
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The simple
inhibit scheme of Figures a and b doesn’t apply, because the
TC output of a given stage is not affected by its own CE.
MODE SELECT TABLE
Inputs
PL CE U/D CP
H
L
L
H
L
H
L
X
X
X
H
H
X
X
Mode
Count Up
Count Down
Preset (Asyn.)
No Change (Hold)
RC TRUTH TABLE
Inputs
PL CE TC* CP
H
L
H
H
H
X
X
H
X
L
X
L
X
X
X
*TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Output
RC
H
H
H
STATE DIAGRAM
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
COUNT UP
COUNT DOWN
FACT DATA
5-2
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