80C42 데이터 시트보기 (PDF) - Intel

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80C42

UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER

Intel 

UPI-C42 UPI-L42

Table 4 UPI Instruction Set (Continued)

Mnemonic

Description

Bytes Cycles

Mnemonic

Description

CONTROL (Continued)

SUSPEND Invoke Suspend Power- 1

2

down mode

NOP

No Operation

1

1

REGISTERS

INC Rr

Increment register

INC Rr

Increment data

memory

DEC Rr

Decrement register

1

1

1

1

1

1

SUBROUTINE

CALL addr Jump to subroutine

RET

Return

RETR

Return and restore

status

2

2

1

2

1

2

FLAGS

CLR C

Clear Carry

1

1

CPL C

Complement Carry

1

1

CLR F0

Clear Flag 0

1

1

CPL F0

Complement Flag 0

1

1

CLR F1

Clear F1 Flag

1

1

CPL F1

Complement F1 Flag

1

1

UPI-C42 UPI-L42 Only

BRANCH

JMP addr

JMPP A

DJNZ Rr addr

JC addr

JNC addr

JZ addr

JNZ addr

JT0 addr

JNT0 addr

JT1 addr

JNT1 addr

JF0 addr

JF1 addr

JTF addr

JNIBF addr

JOBF addr

JBb addr

Jump unconditional

Jump indirect

Decrement register

and jump

Jump on Carry e 1

Jump on Carry e 0

Jump on A Zero

Jump on A not Zero

Jump on T0 e 1

Jump on T0 e 0

Jump on T1 e 1

Jump on T1 e 0

Jump on F0 Flag e 1

Jump on F1 Flag e 1

Jump on Timer Flag

e 1 Clear Flag

Jump on IBF Flag

e0

Jump on OBF Flag

e1

Jump on Accumula-

for Bit

Bytes

2

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Cycles

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

REVISION SUMMARY

The following has been changed since Revision

-003

1 Delete all references to standby power down

mode

The following has been changed since Revision

-002

1 Added information on keyboard controller prod-

uct family

2 Added IHI specification for the UPI-L42

The following has been changed since Revision

-001

1 Added UPI-L42 references and specification

25

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