HI1260JCQ 데이터 시트보기 (PDF) - Intersil

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HI1260JCQ

Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter

Intersil 

HI1260

TABLE 1. INPUT CORRESPONDING TABLE

MSB

11

10

00

INPUT CODE

1111

•

•

•

0000

•

•

•

0000

OUTPUT VOLTAGE

LSB

1 1 VCC + VOFFSET

•

•

•

0 0 VCC + VOFFSET -0.5V

•

•

•

0 0 VCC + VOFFSET -1.0V

Standard Circuit Design Data TA = 25oC, AVCC = DVCC = 5.0V, AGND = DGND = 0.0V

PARAMETER

SYMBOL

TEST CONDITIONS

NOTES MIN TYP MAX UNITS

Crosstalk Among R, G and B

CT

D/A OUT: 1VP-P

RL > 10kΩ

CL < 20pF

fDATA = 7MHz

fCLK = 14MHz

See Figure 5

-

-40

-35

dB

Glitch Energy

GE

VSET – AGND = 0.87V

RL > 10kΩ

fCLK = 1MHz

Digital Ramp Output

See Figure 6

Note 5

-

30

-

pV/s

Rise Time

Fall Time

tr

VSET -AGND = 0.87V

See Figure 4

tf

Note 6

-

5.5

-

ns

Note 6

-

5.0

-

ns

Settling Time

tSET

-

1.6

-

ns

NOTE:

5. Observe the glitch which is generated when the digital input varies as follows:

00111111–01000000

01111111–10000000

10111111–11000000

6. The time required for the D/A OUT to arrive at 90% of its final value from 10%.

Test Circuits and Waveforms

19, 37, 43

DVCC

DGND

D1

D2

D1 - D8

8 (R)

D1 - D8

8 (G)

39 - 42

44 - 47

1-8

ROUT

33

31 GOUT

29 BOUT

V

D8

D1 - D8

9 - 16

27 AVCC

8 (B)

25 VREF

24 VSET

3K

+

-

V

23

33µF

CLK TTL LEVEL

18

20

CLK

HI1260

FIGURE 1. DIFFERENTIAL LINEARITY AND INTEGRAL LINEARITY TEST CIRCUIT

10-6

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