HEF4053B_11 데이터 시트보기 (PDF) - NXP Semiconductors.
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HEF4053B_11 Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4053B
Triple single-pole double-throw analog switch
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25 C.
Symbol
THD
Parameter
total harmonic distortion
Conditions
see Figure 16; RL = 10 k; CL = 15 pF;
channel ON; VI = 0.5VDD (p-p);
fi = 1 kHz
VDD
5V
10 V
15 V
f(3dB)
3 dB frequency response see Figure 17; RL = 1 k; CL = 5 pF;
channel ON; VI = 0.5VDD (p-p)
5V
10 V
15 V
iso
isolation (OFF-state)
see Figure 18; fi = 1 MHz; RL = 1 k; 10 V
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
Vct
crosstalk voltage
digital inputs to switch; see Figure 19; 10 V
RL = 10 k; CL = 15 pF;
E or Sn = VDD (square-wave)
Xtalk
crosstalk
between switches; see Figure 20;
fi = 1 MHz; RL = 1 k;
VI = 0.5VDD (p-p)
10 V
[1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Typ
[1] 0.25
[1] 0.04
[1] 0.04
[1] 13
[1] 40
[1] 70
[1] 50
Max
-
-
-
-
-
-
-
Unit
%
%
%
MHz
MHz
MHz
dB
50
-
mV
[1] 50
- dB
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 2500 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 11500 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 29000 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
11.2.1 Test circuits
VDD
VDD or VSS
VSS
S1 to S3
nZ
E
nY0 1
nY1 2
switch
VSS = VEE
RL
fi
CL D
001aaj904
Fig 16. Test circuit for measuring total harmonic
distortion
VDD
VDD or VSS
VSS
S1 to S3
nZ
E
nY0 1
nY1 2
switch
VSS = VEE
RL
fi
CL dB
001aaj905
Fig 17. Test circuit for measuring frequency response
HEF4053B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
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