HEF4053BT_11 데이터 시트보기 (PDF) - NXP Semiconductors.
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HEF4053BT_11 Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4053B
Triple single-pole double-throw analog switch
VI
negative
pulse
0V
VI
positive
pulse
0V
tW
90 %
VM
10 %
tf
tr
10 %
90 %
VM
tW
PULSE
VI
GENERATOR
VDD VI
VO
DUT
RT
VM
tr
tf
VM
VDD
RL S1
open
CL
VSS
VEE
001aaj903
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 15. Test circuit for measuring switching times
Table 10. Test data
Input
nYn, nZ Sn and E tr, tf
VDD or VEE VDD or VSS 20 ns
VM
0.5VDD
Load
CL
50 pF
RL
10 k
S1 position
tPHL[1]
tPLH
VDD or VEE VEE
tPZH, tPHZ tPZL, tPLZ other
VEE
VDD
VEE
[1] For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD.
HEF4053B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
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