HI5741BIP(2000) 데이터 시트보기 (PDF) - Intersil

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HI5741BIP
(Rev.:2000)

14-Bit, 100 MSPS, High Speed D/A Converter

Intersil 

Timing Diagrams

CLK

HI5741

50%

D13-D0

IOUT

ERROR BAND

V

GLITCH AREA = 1/2 (H x W)

HEIGHT (H)

tPD

tSETT

FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM

WIDTH (W)

t (ps)

FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT

METHOD

CLK

D13-D0

IOUT

tPW1

tPW2

tSU

tSU

tSU

tHLD

tHLD

tHLD

tPD

tSETT

50%

tSETT

tPD

tPD

tSETT

FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

3-5

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