SDA6001 데이터 시트보기 (PDF) - Micronas

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SDA6001

Teletext Decoder with Embedded 16-bit Controller M2

Micronas 

SDA 6000 / SDA 6001

PRELIMINARY DATA SHEET

Version 3.00

Figure 9-6 Sampling of VSync for field detection . . . . . . . . . . . . . . . . . . . . . . 9 - 21

Figure 9-7 Sampling of VSync for field detection in case of delayed VSyncs . 9 - 22

Figure 9-8 Position of Layer1/Layer2 within the display raster . . . . . . . . . . . . 9 - 23

Figure 9-9 Splitting of the frames (Layer1/Layer2) to the display raster . . . . . 9 - 24

Figure 9-10 Position of Layer1/Layer2 within the display raster . . . . . . . . . . . . 9 - 24

Figure 9-11 Splitting of the frames (Layer1/Layer2) to the display raster . . . . . 9 - 25

Figure 10-1 Display Regions and Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6

Figure 10-2 Behavior of Blank Pin for Consecutive Frames in ‘Meshed’ Regions 10 -

7

Figure 10-3 Priority of Layers in Overlapped Layer Mode. . . . . . . . . . . . . . . . . 10 - 8

Figure 10-4 Priority of Layers in Embedded Layer Mode . . . . . . . . . . . . . . . . 10 - 11

Figure 10-5 Format of 1-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

Figure 10-6 Format of 2-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

Figure 10-7 Format of 4-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15

Figure 10-8 Format of 8-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 16

Figure 10-9 Overview on SRU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 16

Figure 10-10 2-bit Pixel Format for Use in Frame Buffer . . . . . . . . . . . . . . . . . 10 - 17

Figure 10-11 8-bit Pixel Format for Use in Frame Buffer . . . . . . . . . . . . . . . . . 10 - 17

Figure 10-12 16-bit Pixel Format (4:4:4:2/TTX) for Use in Frame Buffer . . . . . 10 - 18

Figure 10-13 Internally Generated Flash Signals in Different Flash Phases. . . 10 - 19

Figure 10-14 16-bit Pixel Format (5:6:5) for Use in Frame Buffer . . . . . . . . . . . 10 - 19

Figure 10-15 Overview of GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 20

Figure 10-16 Use of Register Settings to Specify Source Area . . . . . . . . . . . . 10 - 25

Figure 10-17 Use of Register Settings to Specify Destination and Clipping Area 10 - 28

Figure 10-18 Result for a Non-italic Transferred Memory Area in Frame Buffer 10 - 28

Figure 10-19 Result for a Italic Transferred Memory Area in Frame Buffer . . . 10 - 29

Figure 10-20 Result for an Italic Transferred Memory Area at D/A Converter Output 10

- 29

Figure 10-21 Organization of GAIs in the External SDRAM . . . . . . . . . . . . . . . 10 - 33

Figure 10-22 GAI Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 34

Figure 12-1 Block Diagram of Digital Slicer and Acquisition Interface . . . . . . . 12 - 6

Figure 12-2 VBI Buffer: General Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 12

Figure 14-1 H/V - Sync-Timing (Sync-master mode) . . . . . . . . . . . . . . . . . . . 14 - 14

Figure 14-2 VCS -Timing (Sync-master mode) . . . . . . . . . . . . . . . . . . . . . . . . 14 - 14

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