DS2188(1998) 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2188
(Rev.:1998)

T1/CEPT Jitter Attenuator

Dallas Semiconductor -> Maxim Integrated 

DS2188

PIN DESCRIPTION Table 1

PIN

SYMBOL

1

DJA

TYPE

I

2

RPOS

I

3

RNEG

I

4

RCLK

I

5

BDS

I

6

TEST

I

7

XTAL OUT

O

8

VSS

–

9

XTAL1

I

10

XTAL2

O

11

BL

O

12

RST

I

13

RRCLK

O

14

RRNEG

O

15

RRPOS

O

16

VDD

–

DESCRIPTION

Disable Jitter Attenuation. When high, jittered data and clock at

RPOS, RNEG, and RCLK are passed directly to RRPOS,

RRNEG, and RRCLK.

Receive Positive Data Input. Jittered data input. Sampled on the

falling edge of RCLK.

Receive Negative Data Input. Jittered data input. Sampled on

the falling edge of RCLK.

Receive Clock Input. Jittered input 1.544 MHz or 2.048 MHz

clock.

Buffer Depth Select.

0 = 128 bits

1 = 32 bits

Test Input. In normal applications, this pin should be tied low.

When tied high, used to verify free running frequency of XTAL.

Crystal Frequency Output. Buffered output of the 4X crystal con-

nected to XTAL1 and XTAL2.

Ground. 0.0 volts.

Crystal Connections. In T1 environments, connect a 6.176 MHz

crystal to these pins. In CEPT environments, connect a 8.192 MHz

crystal to these pins.

Buffer Limit. Transitions high when the buffer fills or empties to

within either 4 bits (BDS=0) or 2 bits (BDS=1) of its capacity. Indi-

cates that the jitter at RCLK is greater than 120 UIpp (BDS=0) or

28 UIpp (BDS=1).

Reset. Negative–edge triggered; a high–low transition will recent-

er the buffer. Activation of this pin may corrupt data through the

DS2188.

Receive Reference Clock. Dejittered 1.544 MHz or 2.048 MHz

clock.

Receive Reference Negative Data Output. Dejittered data out-

put. Updated on the rising edge of RRCLK.

Receive Reference Positive Data Output. Dejittered data out-

put. Updated on the rising edge of RRCLK.

Positive Supply. 5.0 volts.

022798 5/11

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