CXK581000AM-55LL 데이터 시트보기 (PDF) - Sony Semiconductor

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CXK581000AM-55LL

131072-word × 8-bit High Speed CMOS Static RAM

Sony Semiconductor 

CXK581000ATM/AYM/AM/AP

• Write cycle (2) : CE1 control

Address

OE

tAS

CE1

CE2

WE

Data in

tWC

tAW

tCW

tCW

tWR1 (∗3)

tWP

tDW

tDH

Data valid

Data out

• Write cycle (3) : CE2 control

Address

OE

CE1

tAS

CE2

WE

Data in

High impedance

tWC

tAW

tCW

tOCW

tWP

tWR1 (∗3)

tDW

tDH

Data valid

Data out

High impedance

∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.

∗2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition.

∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until

the end of the write cycle.

–7–

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