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STPCC4HEBC

X86 Core PC Compatible Information Appliance System-on-Chip

STMicroelectronics 

STPC® CONSUMER-II

s X86 Processor core

s Fully static 32-bit five-stage pipeline, x86

processor fully PC compatible.

s Can access up to 4 GB of external memory.

s 8 Kbyte unified instruction and data cache

with write back and write through capability.

s Parallel processing integral floating point unit,

with automatic power down.

s Runs up to 100 MHz (x1) or 133 MHz (x2).

s Fully static design for dynamic clock control.

s Low power and system management modes.

s Optimized design for 2.5 V operation.

s SDRAM Controller

s 64-bit data bus.

s Up to 100 MHz SDRAM clock speed.

s Integrated system memory, graphic frame

memory and video frame memory.

s Supports 2 MB up to 128 MB system

memory.

s Supports 16-, 64-, and 128-Mbit SDRAMs.

s Supports 8, 16, 32, 64, and 128 MB DIMMs.

s Supports buffered, non buffered, and

registered DIMMs

s Four-line write buffers for CPU to SDRAM

and PCI to SDRAM cycles.

s Four-line read prefetch buffers for PCI

masters.

s Programmable latency

s Programmable timing for SDRAM

parameters.

s Supports -8, -10, -12, -13, -15 memory parts

s Supports memory hole between 1 MB and

8 MB for PCI/ISA busses.

s 2D Graphics Controller

s 64-bit windows accelerator.

s Backward compatibility to SVGA standards.

s Hardware acceleration for text, bitblts,

transparent blts and fills.

s Up to 64 x 64 bit graphics hardware cursor.

s Up to 4MB long linear frame buffer.

s 8-, 16-, 24- and 32-bit pixels.

s Drivers availables for various OSes.

s CRT Controller

s Integrated 135 MHz triple RAMDAC allowing

for 1280 x 1024 x 75 Hz display.

s Requires external frequency synthesizer and

reference sources.

s 8-bit, 16-bit, 24-bit pixels.

s Interlaced or non-interlaced output.

s Requires no external frequency synthesizer.

s Requires only external reference source.

s Video Input port

s Accepts video inputs in ITU-R 601 mode.

s Optional 2:1 decimator

s Stores captured video in off setting area of

the onboard frame buffer.

s Video pass through to the TV output for full

screen video images.

s HSYNC and B/T generation or lock onto

external video timing source.

s Video Pipeline

s Two-tap interpolative horizontal filter.

s Two-tap interpolative vertical filter.

s Colour space conversion (RGB to YUV and

YUV to RGB).

s Programmable window size.

s Chroma and colour keying for integrated

video overlay.

s Video Output

s NTSC-M; PAL-B, D, G, H, I, M, N encoding.

s ITU-R 601 encoding with programmable

colour subcarrier frequencies.

s ITU-R 656 video output signal interface.

s Four analog outputs in two configurations:

- R,G,B + CVBS

- C,YS,CVBS1 + CVBS2

s Flicker-free interlaced output.

s Programmable two tap filter with gamma

correction or three tap flicker filter.

s Interlaced or non-interlaced operation mode.

s Progressive to interlaced scan converter.

s Cross colour reduction by specific trap

filtering on luma within CVBS flow.

s Power down mode available on each DAC.

2/93

Release 1.5 - January 29, 2002

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