W48S101-04H 데이터 시트보기 (PDF) - Cypress Semiconductor
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W48S101-04H Datasheet PDF : 12 Pages
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PRELIMINARY
W48S101-04
48MHz0:1 Clock Output (Lump Capacitance Test Load = 20 pF = 66.6/100 MHz)
Parameter
Description
f
Frequency, Actual
fD
Deviation from 48 MHz
m/n
PLL Ratio
tR
Output Rise Edge Rate
tF
Output Fall Edge Rate
tD
Duty Cycle
fST
Frequency Stabilization
from Power-up (cold start)
Zo
AC Output Impedance
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 66.8/100 MHz
Min. Typ. Max.
48.008
+167
57/17
0.5
2
0.5
2
45
55
3
40
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Freq. Mask
Code
W48S101
-04
Document #: 38-00853
Package
Name
H
Package Type
48-pin SSOP (300 mils)
11
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